But 802.11a has problems of its own. One is simply that it is a challenging technology: It's nontrivial to pack a 5-GHz radio transceiver, IF stages and OFDM baseband into a package anywhere close to the size, price and power consumption of a palmtop computer, let alone an organizer.

A second, equally serious problem is in the OFDM coding itself. The bit stream produced by the coding scheme has an inherently high-12- to 14-dB-ratio of peak-to-average power. That puts a strain on the radio design and the power consumption.

Two recently announced chip designs from two fabless startups are attacking the problems with architectural innovation.

IceFyre Semiconductor (Ottawa) is grappling with the problem of peak-to-average power ratio. The company has developed a technique-also being explored elsewhere in the industry, we are told-for recoding the bit stream going into the power amplifier. If you can reduce those signal peaks without changing the underlying phase relationships in the bit stream, you can substantially reduce the peak-to-average ratio: from 12 dB to 9 dB, IceFyre claims.

That requires some interesting signal processing at a rate too high to be practical in a programmable DSP. So IceFyre has developed a flow-through, state-machine-based signal engine to transform the transmit bit stream.

Reducing the peak excursions meant reducing the slew rate and instantaneous power requirements on the power amplifier. That, according to IceFyre, put the power amp design within the range of advanced CMOS, eliminating the need for a separate SiGe or GaAs power amplifier chip.

While IceFyre is focusing on the transmit side, Resonext (San Jose, Calif.) is working on the receive side. To reduce size, power and the large number of external passive components in the 5-GHz receiver, the company has produced a zero-IF architecture for 802.11a systems.

Company designers admit that eliminating the IF at that frequency, with a coding scheme as delicate as OFDM, was a significant undertaking. It required designing a mixer that could downconvert all the way from 5 GHz to baseband in one step. And that required attention to every conceivable source of error in the design.

Just getting a VCO to run at that frequency in silicon-let alone with the necessary precision to produce a stable baseband signal-was a huge challenge. But one of the most impossible problems to eliminate, according to the design team, was dc offset in the quadrature section.

Just improving the circuitry didn't do the job.

Resonext turned to architectural innovation to attack the problem. The designers worked out a way to extract digital feedback from the baseband circuitry and employ it back in the RF stage to, among other things, nearly eliminate the offset problem. The technique was an enabling factor in achieving the zero-IF design, which in turn enabled such apparently unrelated gains as a sharp reduction in external components.

Hypercritical port
The design group at API Networks has gone through an interesting evolution. Once happily thriving as the respected Alpha processor design team within Digital Equipment Corp., the group found itself spun off as an independent design shop during the dismemberment of DEC, with parts going to Intel-which had no interest in Alpha-and Compaq-which did not want to be in the CPU business.

As irony would have it, the group found itself first supplying Alpha-targeted core logic to AMD in support of that company's assault on the X86 server market. An evolutionary step beyond that led to the joint development of an entirely new point-to-point board-level interconnect scheme, HyperTransport. So now, the design group, alias Alpha Processors Inc., alias API Networks, finds itself the fabless semiconductor supplier of HyperTransport silicon.

And that is no mean challenge. HyperTransport is based on clusters of 1.6-Gbit/s differential pairs operating in voltage mode with 600-millivolt swings. The interface is intended to be wide, as in multiple bytes, and to be integrated onto core logic chips.

Designing such a physical-layer interface was "not for the faint-hearted," according to president and CTO Gerry Talbot. One of the first issues the team faced was that the pairs required 100-ohm termination. And at these frequencies, the termination had to be on-chip, plunging the team into resistor design.

In addition, noise was a huge issue. The PHY layer ended up with its own supply rails, decoupling caps and isolation rings.

All of this created a substantial modeling problem. In fact, the package-custom designed by the team to meet the needs of the PHY-had to be modeled right along with the pad ring. Fortunately, the entire PHY-plus-package combination lies within the range of reasonable Spice runs.

Extraction was another matter. Since this was very much an analog design, RC extraction was not just a matter of screening for excessive parasitics, but a measure of critical circuit parameters. And it proved problematic.

Star-RC proved one solution, according to the team. But it needed intervention to produce useful results.

Left to its own devices, the tool produced quite good capacitor values, the team reported. But on resistors, it went nuts. "We would get literally tens of thousands of half-ohm resistors scattered everywhere. We had to guide the extraction very carefully to tell it when a resistor mattered and when it didn't, or we got unsimulatable results," Talbot said.

Fast serial world
Add another name to the list of vendors coping with very high-speed, low-voltage differential signaling in fast serial interfaces: Marvell Networks (Sunnyvale, Calif.).

In Marvell's case, the application is the serial ATA specification being driven by an Intel-backed group in the computer business. The idea is great: a single, very fast serial line to replace the big, power-hungry and fragile ribbon cable required by the near-ubiquitous ATA disk-drive interface spec. Of course, there is the small matter of avoiding the royalties that would be required by a 1394 interface as well.

From a chip designer's point of view, the interface presents an increasingly familiar set of problems: very low voltage swings, very fast data rates-1.5 GHz-and sensitive analog signals-250-mV swings-until you do clock and data recovery and deserialization.

In fact, the physical layer is very similar to the Fibre Channel spec, according to Marvell. The company was able to lever Fibre Channel work done at Galileo Technology in the design. But perhaps the largest difference here is the application, and hence the design environment. Marvell sees the serial ATA interface getting integrated into core logic and storage-area network controllers: intense digital environments. Worse yet, the connection has to be terminated on a disk-controller IC, already a very challenging mixed-signal chip with both highly sensitive analog amplifiers and fast DSP circuits. So the physical-layer core has to be digital friendly. And that is no small requirement.

The design also has to be price friendly, and that created one of the big design issues by itself, according to project leader Po Chien Chang. The serial ATA spec calls for a crystal-stabilized oscillator. But Marvell, knowing the spending habits of disk-drive vendors, knew that to be a nonstarter: These guys buy ceramic resonators, not crystals. Hence the design had to achieve adequate jitter, about 250 ppm, with a ceramic resonator that had something like a 1.5 percent jitter offset. That required a second-order loop filter, entirely possible with modern techniques. But that, in turn, introduced unacceptable latency. So the adder in the second-order loop became a critical component, custom designed and routed by hand.

The other critical issue was obviously noise. The crusade for noise immunity started with separate analog power buses and a local voltage regulator in each analog block on the chip. Other measures included hand-routing clocks away from potential sources of digital noise and extensive shielding of sensitive interconnect lines.

That left the problem of substrate noise, which remains one of the hardest problems to quantify in mixed-signal design. For that, Marvell turned to its own experience, creating an isolation ring structure around the analog microcore. Chang believed that the tools at hand were inadequate to characterize the isolation for the 0.18-micron process, so he relied on experience. There's something to be said for having been down a road before.

http://www.isdmag.com